1. Field of the Invention
This invention relates generally to the execution of decimal alphanumeric instructions by a commercial instruction processor of a data processing system and more specifically to apparatus that indicates operand alignment in response to data descriptor information.
2. Description of the Prior Art
The number of steps required to execute a decimal alphanumeric instruction are normally reduced if the operands involved which are read from main memory are aligned relative to each other. Some instructions such as a decimal add instruction require the two operands have the least significant decimal digits aligned. A decimal alphanumeric compare instruction requires that the two operands have the high order characters aligned. For the decimal add instruction, successive operand words are transferred from main memory low order word first and for the decimal alphanumeric compare instruction, successive operand words are transferred from main memory high order word first.
The operands may be in string decimal form, typically two byte positions per word, or in packed decimal form, typically four decimal digit positions. The operand high order or low order byte or digit may be stored in either a byte position or any digit position of the word.
The characteristics of the operand may be defined by words called data descriptors and are usually transferred from memory following the instruction word. The data descriptor information may include a binary bit indicating a string or packed decimal operand, a binary field indicating the number of bytes or digits in the operand, the position in the high order word of the high order byte or digit, and the location of the sign character, a trailing, leading or "overpunched" sign.
Apparatus for receiving data descriptors and generating signals for aligning the operands is described in U.S. Pat. No. 4,276,596 issued June 30, 1981 entitled "Short Operand Alignment and Merge Operation", and U.S. Pat. No. 4,240,144 issued Dec. 16, 1980 entitled "Long Operand Alignment and Merge Operation" which describe apparatus which is responsive to data descriptor information for generating signals used in aligning the operands. The apparatus for generating the alignment signals included a number of logic elements including registers, adders and control circuits.